FIG. 4 shows a graph which shows a specific capacitance, i.e. a capacitance per unit length (farad/μm) as a function of a radius ratio V of a cylindrical capacitor, the capacitance per unit length being illustrated on the cylinder axis. A radius ratio V is therefore: V=r1/r2 in accordance with FIG. 4(b). FIG. 4(a) shows the corresponding capacitance curves, i.e. a first capacitance curve 403 for a dielectric with a low dielectric constant, for example k=4, and a second capacitance curve 404 for a dielectric with a high capacitance, for example k=11. The curve for the specific capacitance 402 is in each case plotted against the radius ratio V=r1/r2, which is defined in accordance with FIG. 4(b). FIG. 4(b) illustrates a cross section through the cylinder perpendicular to its axis.
For capacitive elements of this type to be used as memory cells in DRAMs (Dynamic Random Access Memories), it is necessary to provide a minimum capacitance for storing electric charge.
It is known to the average person skilled in the art that the required capacitance to maintain a signal that can be measured when the memory cell is read and is higher than a thermal noise level, depending on the particular embodiment of the DRAM, must be at least 29 to 35 fF (femtofarad), i.e. 30×10−15 farad. As shown in FIGS. 4(a) and (b), there are limits on the extent to which a capacitance can be increased by varying the radius ratio V. This means that it is not possible to obtain a radius ratio V of the order of magnitude of 1, since a minimum thickness of the dielectric forming the capacitor has to be provided.
Furthermore, it is not expedient to provide arrangements extending along the axis of the cylindrical capacitor in order to increase the capacitance. Very long or high cylindrical capacitors can only be produced with very great difficulty or using extremely expensive production processes, for manufacturing technology reasons. Since the capacitive elements which form the memory cells are produced by etching trenches or cups into a silicon substrate or by providing a cup in a structure above the substrate surface in a conventional way, conventional methods have attempted to etch or pattern trenches or cups of this type down to ever greater depths or to “roughen” their side walls in order to achieve larger electrode surface areas and therefore higher capacitances in the capacitive elements.
Since capacitive elements of this type are fabricated using lithographic processes, conventional processes are not expediently suitable for providing a sufficient increase in capacitance.